Design-Reuse28d
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process View Data Block of DDR3/DDR3L/DDR2 ...
Design-Reuse4y
DDR4/ DDR3/ DDR3L Combo PHY IP - 1600Mpbs (Silicon Proven in TSMC 28HPC+)
This DDR (Double Data Rate) PHY IP supports DDR3/DDR3L/DDR4, provides low latency, and enables up to 1600Mbps throughput. The PHY IP is silicon proven and designed for ease of integration and faster ...